OpenRISC can be used for commercial purposes
FPGA soft core
A soft core is a processor, a microcontroller or a digital signal processor that is integrated as a virtual unit in an FPGA or ASIC. Thus, in theory, any processor can be added to a digital circuit design, becoming a de facto hard core in an ASIC. In the FPGA, this consists of pure user logic, which is configured accordingly. Alternatively, there are real hard cores in FPGAs that have already been placed on the chip. Some manufacturers also make it possible to convert a complete FPGA design into an ASIC, which in practice also creates a hard core.
As a rule, soft cores in FPGAs are used to carry out complicated tasks that overwhelm a classic state machine or make it ineffective, but which at the same time do not place too high demands on speed. Often, SCs are integrated into FPGAs at a later date if, in the course of expanding the scope of functions, it turns out that tasks are becoming more complex and intelligent management is required.
Comparison of soft cores and hard cores
- Flexible application, the FPGA can provided with a SoftCore if necessary; However, no chip area is wasted in advance for a possibly unused hard core (cost advantage)
- Some softcore can be configured very flexibly (16/32 bit data paths, additional modules, special user commands, etc.)
- Depending on the application, small soft cores can be placed and used in parallel multiple times in the FPGA, thereby increasing the data processing capacity (e.g. an RX processor and a TX processor)
- Lower speed
- Higher heat dissipation
A soft core is often used for display controls or the configuration of peripheral components via I2C. In this way, existing C code can often also be used.
The achievable clock frequencies are heavily dependent on the FPGA type and the FPGA load (free logic resources). With soft cores, therefore, a maximum data throughput rate of the order of 10-20Mbps can typically be achieved.
A large number of freely available soft CPUs are available on OpenCores.org. The existing palette ranges from replicas of existing processors, such as the AVR, PIC or MIPS, to our own developments, such as the "16 Bit Microcontroller" (c16), which is specially optimized for FPGAs and comes with its own RTOS. Another is e.g. B. the 32-bit OpenRisc 1000, for which a version of the GNU tools for software development are available.
The aim here is to provide a brief overview of existing softcores, for which software support exists and which services can be expected. Often the greatest softcore is of no use if it cannot be programmed accordingly. A system builder is available for LatticeMico32, MicroBlaze and NIOS. This allows the processor and peripherals to be configured easily and clearly.
8 bit soft cores 
|Surname||optimized for||Source code||max. program memory||programming||Toolchain||power||License / price||Web link|
|AX8||not applicable||yes, VHDL||2k (8k)||asm, C, Basic, Ada ...||GCC / WinAVR, ...||like AT90S2313 with 30-50MHz||OpenCores|
|Xmega / ATmega / ATtiny||not applicable||yes, verilog||128 KiB||C, C ++, Asm||GCC, Clang||GPL|||
|T51||not applicable||yes, VHDL||64k||asm, Basic, C, ...||sdcc, MCS-Basic, ...||single cycle 8051, e.g. B. 40 MHz on Spartan3||OpenCores|
|8051 IP Core||not applicable||yes, VHDL||64k||asm, Basic, C, ...||sdcc, MCS-Basic, ...||1-4 cycle 8051||open IP core||Oregano Systems|
|LatticeMico8||Lattice||yes, Verilog & VHDL||asm, C.||GNU toolchain||open IP core||Lattice|
|PicoBlaze||Xilinx||yes, VHDL||2k (1024 commands)||asm (DOS / dosbox)||according to Xilinx 100 MIPS||Xilinx Reference Design License||Xilinx|
|PacoBlaze||not applicable||yes, verilog||like PicoBlaze||asm (written in Java)||KCAsm||like Picoblaze||modified BSD license||PacoBlaze|
|panda||not applicable||yes, VHDL||64k||asm||HASM, Builder SW||depending on the configuration||Free IP, Boost||LogicSolutions|
|Proteus||not applicable||yes, VHDL||64k||asm||HASM, Builder SW||depending on the configuration||Free IP, Boost||LogicSolutions|
|embedded Z8 (UB8820)||XILINX, ASIC syn.||yes, VHDL||64k||asm||Macro assembler AS||depending on the configuration||Free IP||embeddedZ8 site|
|bo8||yes, VHDL||n * 64k||asm||Approved||bo8|
It is a very small but very powerful microprocessor.
- only 76-93 slices resource requirements
- 16 8-bit registers
- 1024 commands program memory (version for Spartan-II only 256 commands)
- 18-bit commands, RISC (version for Spartan-II has 16-bit commands)
- All Commands last two bars
- Interrupt support
- 8-bit IO bus
- Indirect addressing possible
- Program memory can be expanded by switching banks
- Assembler available as command line program
- Development environment pBlazeIDE available with integrated assembler
- Fast program download via JTAG during development
- 37..102 MIPS, depending on the FPGA family
The AX8 core is almost the same as an Atmel AT90S2313. It still lacks hardware units such as EEPROM, watchdog and the various powerdown modes.
- Resource requirements: ~ 1400 Xilinx slices
- achievable speed on a Spartan3-1000: 50 MHz
- WinAVR or similar can be used as a tool chain without any problems
The ROM description must be adapted so that XST can generate a block RAM (a suitable hex2rom is available here: hex2rom).
The core can easily be expanded with memory (8KByte ROM), an EEPROM (up to 64KByte), two ports and a watchdog. The AX8 then corresponds to an AT90S8535, with the exception of the other timers / counters and the missing SPI interface.
As with the Picoblaze, the ROM content can be updated via the JTAG interface for development purposes. Thus, new software can be tested without having to re-synthesize the design. For this you need the tools hex2svf, svf2xsvf and xsvfplayer. In the FPGA, a state machine at the JTAG port then fills a dual-port RAM (ROM :-))
In contrast to newer AVR controllers like the ATMega8, the AX8-Core lacks commands like MOVW, MUL and FMUL. Hardware units such as I2C and extended timers are also missing. The greatest limitation, however, is the maximum program memory space of 8KByte. More memory requires major changes to the core's VHDL code.
The AVR8 Soft Processor core is an AVR instruction set compatible processor that is optimized to run on the Butterfly Flight or Butterfly Light FPGA hardware. It is based on the ATmega103 processor and includes a full toolchain to compile and run C code developed with avr-gcc.
Softcore for AVR Xmega / ATmega / ATtiny by Iulian Gheorghiu 
In addition to the core itself, a number of AVR peripheral components are implemented. The code is under GPL.
An older version of it is also available from OpenCores, where the pure processor code is still under a 1-clause BSD license (but the peripherals are already GPL there).
A graphical builder software is available to generate a system including peripherals without having to write VHDL. Some peripherals (timers, ports, etc.) are already integrated, your own peripherals can be integrated into the software. The processor is highly configurable (e.g. switching individual instructions on / off).
The processor can be perfectly adapted to the project with over 20 generics. For example, word width, instructions, pipelining and registers can be adjusted. There is also JTAG debugging software for the processor, which also enables multiple processors in one chip to be debugged. Custom instructions are also supported. Proteus has two separate wishbone interfaces for data and instructions and is 100% manufacturer-independent. In its smallest configuration, Proteus requires fewer than 300 LUTs.
embedded Z8 (UB8820 / UB8840) 
Freely configurable microcontroller core which is based on the architecture of the UB8820 / ... (thus corresponding to the z8)
- configurable number of register sets
The CPU bo8 is part of an on mikrocontroller.net presented overall project. It has a complete instruction set with 256 OpCodes. The calculation of the duration of command sequences by counting cycles is very simple. The CPU can address an unlimited number of 64KByte pages. The lack of interrupts and the lack of information about the maximum clock frequency are disadvantageous.
16 bit soft cores 
|Surname||optimized for||Source code||programming||Toolchain||power||License / price||Web link|
|NEO430||generic||Yes, VHDL||asm, C, C ++, ..||TI MSP430-gcc (Windows, Linux / Cygwin)||4-12 cycles per instruction||LGPL||neo430 @ GitHub|
|OpenMSP430||FPGA & ASIC||Yes, Verilog||asm, C, C ++, ..||MSPGCC (Windows, Linux / Cygwin)||1-6 cycles per instruction||BSD||OpenMSP430 @ OpenCores.org|
|TG68||Yes, VHDL||asm, C, C ++, ..||GCC, (68k-compatible)||LGPL||tg68 @ OpenCores.org|
|UCore||Altera||VHDL||Assembler||Assembler, emulator||single cycle per instruction||Article  HP |
- MSP430-ISA compatible (uses TI MSP430-gcc compiler), 16-bit
- UART / SPI EEPROM bootloader
- Various sample programs and tutorials
- Hardware (adaptable): Timer, SPI & UART, Parallel IO, Watchdog, Wishbone Interface, ...
- Performance: 4..12 clock cycles per instruction, ~ 116MHz (Altera Cyclone IV EP4CE22F17C6N)
- Resource requirements: 700..1200 LE's on Altera Cyclone IV
- Data sheet (on GiHub): NEO430.pdf
- MSP430 compatible (uses MSPGCC compiler), 16-bit RISC
- FPGA and ASIC tested
- Hardware (customizable): 16x16 hardware multiplier, watchdog, GPIO, TimerA, generic templates
- two-wire serial debug interface with support of the MSPGCC GNU Debugger (GDB)
- Performance: 1..6 clock cycles per instruction
- Resource requirements: Xilinx: 1650 LUTs / Altera: 1550 LEs / ASIC: 8k gate
- Datasheet (on opencores.org): openMSP430.pdf
- 68000 compatible
- Resource requirements: ~ 2700 Xilinx Slices, ~ 4000 LC's on Altera Cyclone II
32 bit soft cores 
|Surname||optimized for||Source code||programming||Toolchain||power||License / price||Web link|
|HiCoVec vector processor||Xilinx Spartan 3A||yes, VHDL||asm, C.||GCC, HiCoVec assembler||Flexible vector unit||GPL||HS-Augsburg|
|LatticeMico32||Lattice, but see soc-lm32||yes, verilog||asm, C, C ++||GCC, MSB||open IP core||Lattice|
|Leon||Yes, VHDL||asm, C, C ++||GCC (SPARC-compatible)||GPL||Gaisler Research|
|MicroBlaze||Xilinx||No||asm, C, C ++||GCC, EDK||EDK $ 500 / year||Xilinx|
MicroBlaze at Wikipedia
|MicroBlaze MCS||Xilinx||No||asm, C, C ++||GCC, SDK||free of charge||Xilinx|
|NEORV32 (RISC-V)||generic||yes, VHDL||asm, C, C ++||GCC||BSD||GitHubOpenCores|
|NIOS II||Altera||No||asm, C, C ++||GCC, SOPC, EDS||with Nios II Eval-Kit from $ 400, or $ 3000 - Nios II / e core free (12/2009)||Altera|
|OpenRISC||Yes, Verilog||asm, C, C ++, ..||GCC||OpenCores|
|plasma||Yes, VHDL||asm, C, C ++||GCC (MIPS-compatible)||GPL||OpenCores.org|
|CORN||Yes, VHDL||asm, C, C ++||GCC||Creative Commons CC BY-NC 3.0 with exception commercial applicants have to pay a license fee|||
|Propeller 2||Yes, VHDL||C,||Parallax IDE||GPL3|||
|Cylinder CPU (ZPU)||Yes, VHDL||asm, C, C ++||GCC||FreeBSD / GPL||Zylin.com|
|f32c (RISC-V / MIPS)||Lattice, Altera, Xilinx||Yes, VHDL||asm, C, C ++||GCC, Arduino IDE||1.63 DMIPS / MHz, 3.06 CoreMark / MHz||BSD||f32c|
|PULPino (RISC-V)||ASIC, Xilinx||Yes, SystemVerilog||asm, C, C ++, ..||GCC, LLVM||WITH||pulp platform|
A first impression of the performance of the 32 bit SoftCores is given e.g. B. the master's thesis "Evaluation of synthesizable CPU cores" from 2004. This compares the Leon 2, MicroBlaze and OpenRISC 1200 with each other.
Lattice Mico32 and soc-lm32 
Mico32 is a 32 bit pipelined RISC CPU. The is under an open source license and is completely in the Verilog source code. Both the CPU architecture and the resource requirements are comparable to the MicroBlaze from Xilinx, but it is an independent development by Lattice.
- Resource requirement: ~ 1600 slices (Lattice / Xilinx)
- Reaches approx. 80-116MHz on ECP2 and XP2 devices from Lattice and approx. 100 MHz on Spartan3 generation FPGAs,
- Configurable D and I caches (from BRAM or Distributed RAM)
- 2 Wishbone interfaces: For data load & store and instruction fetch
- System builder with automatically created Wishbone arbiters
- No limit on the number of Wishbone buses used
- Complete GNU toolchain from binutils, gcc and gdb
- Eclipse development environment, managed C and C ++ development
- Automatic driver creation by the system builder
- Simultaneous use of the logic analyzer and debugger in Lattice blocks
In addition to the original, which can be downloaded from Lattice, and whose toolchain is initially designed for Windows with Lattice FPGAs, there is also soc-lm32. soc-lm32 is a port to Altera and Xilinx components and uses a Makefile-based workflow.
A port of uC-Linux commissioned by Lattice is available (http://www.theobroma-systems.com/mico32/).
Disadvantages: up to now there is no version with FPU (can be flange-mounted via Wishbone as peripheral) or MMU.
Comment: single precision arithmetic modules in VERILOG (fadd, fsub, fmul, fdiv, flog, fexp and conversion) are available at: https://www.linkedin.com/in/till-wallendorf-32754b134
This processor core is completely SPARC V8 compatible - any SPARC compiler can be used (e.g. bcc,). In addition to the core itself, there is also a wide range of peripherals available in the form of VHDL components. AMBA (AHB + APB) is used as an on-chip interconnect.
- Resource requirements: ~ 4000 Xilinx slices, 10 BRAMs (minimal configuration)
- Reaches approx. 50 MHz on Spartan3 generation FPGAs
MicroBlaze & replicas 
MicroBlaze is a core made available by Xilinx especially for their FPGAs. It can be instantiated and configured with the XPS software, among other things. The software is developed in C using the EDK software.
Microblaze, unlike PicoBlaze, is commercial and requires a license. However, starting with ISE 13.4. released a lightweight Microblaze - MicroBlaze MCS - which can be used free of charge for all Xilinx FPGA's (possibly except for prehistoric relics like Spartan XL ?!):
This is generated with the CoreGen instead of the EDK, Xilinx provides an SDK for programming (C / C ++).
RISC-V based 32-bit soft-core microcontroller, "big brother" of the NEO430, available on GitHub
- Customizable hardware configuration (via generics)
- Platform-independent description in VHDL (tested on Intel, Xilinx and Lattice FPGAs)
- Optional peripheral modules: timer, watchdog, SPI, UARTs, I²C, TRNG, NCO, native NeoPixel interface, GPIO, PWM, bootloader, internal memory / caches, Wishbone / AXI4-Lite bus interface
- Software framework (documentation on GitHub pages)
- data sheet available (pdf)
- 0.9 Coremarks / Mhz at ~ 2700 (CPU) Intel Cyclone IV LUTs at 124 MHz
|A. (atomic)||Atomic memory access (optional)|
|B. (bit manipulation)||Bit manipulation instructions (optional)|
|C. (compressed)||16-bit compressed instructions (optional)|
|E. (embedded)||Reduced register file - 16 instead of 32 registers (optional)|
|I. (integer-base)||Integer base ISA|
|M. (mul-div)||Hardware multiplier and divider (optional)|
|U (user mode)||User mode with reduced rights (optional)|
|Zfinx (floating point)||32-bit single-precision floating point hardware (optional)|
|Zicsr (privilege-base)||Control and status registers - e.g. for interrupts / traps / exceptions (optional)|
|Zifencei (I-sync)||Instruction stream synchronization - e.g. for self-modifying code (optional)|
|PMP||Physical memory protection (optional)|
|HPM||Hardware Performance Monitors - e.g. for benchmarking (optional)|
Complete open source package consisting of SoftCore, IDE and debugging of the Propeller 2 uC: http://de.wikipedia.org/wiki/Parallax_Propellerhttp://www.parallax.com/microcontrollers/propeller-1-open-source
64 bit soft cores 
OpenSPARC T1 
128 bit soft cores 
In the meantime, 128-bit soft cores are also used as RISC processors for special applications. Please refer:
Web links 
First steps with Leon3, OpenRISC 1200, Nios II and MicroBlaze: http://www.rte.se/blog/blogg-modesty-corex/index
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